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| FXL3SD206 -- Level Shifting Voltage Translator March 2009 FXL3SD206 Level Shifting Voltage Translator Two-Port SDIO MUX/DEMUX with Three Configurable Power Supplies for SDIO Device Port Expansion Features Bi-Directional Interface between Two Levels: 1.65 to 3.6V Fully Configurable: Inputs and Outputs Track VDD Flexible and Programmable VDD of B and C Ports Non-Preferential Power-up; either VDD Can Power Up First Output Remains in 3-State until Active VDD Level is Reached Output Switches to 3-state if either VDD is at GND Power-off Protection Bus-Hold on Data Input Eliminates the Need for SDIO Pull-up Resistors 2:1 MUX/DEMUX of SDIO Devices in 24-Terminal Micro-MLP Package (2.5mm x 3.4mm) Direction Control is Automatic Power Switching Time (VDD_HI to VDD_LO or Reverse) is Less than 1.7s 60Mbps Throughput ESD Protection Exceeds: 12KV HBM (A, B, and C port I/O to GND) (per JESD22-A114) 1KV CDM (per ESD STM5.3) Description FXL3SD206 is a voltage translator with multiplexing and de-multiplexing functions for SDIO devices. It is designed for voltage translation over a wide range of input and output levels, from 1.65V to 3.6V. The multiplexing/de-multiplexing function of this device allows expansion of a host SDIO interface to two SDIO peripheral devices. When selected, each SDIO peripheral can communicate with the host through the same host interface. An alternative application allows two host devices to interface with a single SDIO peripheral. Port A is intended to connect to a host device and the voltage level tracks the VDDA. Ports B and C are intended to connect to peripheral devices. Peripheral I/O voltage levels track either VDD_HI or VDD_LO as determined by the VDD_SEL pin. During normal operation, VDD_HI must be greater than or equal to VDD_LO. The CH_SEL, VDD_SEL, and OE pins are referenced to VDD_CON. Channel communication from either Port A to Port B or Port A to Port C is controlled by the CH_SEL pin. The selected channel remains in 3-state until the VDD of each side reaches an active level and the OE pin reaches a valid high. Internal power-down circuitry places the selected channel of the device in 3-state if either side VDD removed. The direction of data is controlled automatically by the device. No direction control pin is required. The device senses input signals on any port automatically and transfers the data to the corresponding output. Applications SDIO Devices Cell Phone, PDA, Digital Camera, Portable GPS Ordering Information Part Number FXL3SD206UMX Operating Temperature Range -40 to +85C Eco Status Green Package 24-Pin, Micro-MLP, Quad, .6mm Thick, 2.5mm x 3.4mm Body Packing Method Tape & Reel For Fairchild's definition of "green" Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. (c) 2009 Fairchild Semiconductor Corporation FXL3SD206 * Rev. 1.0.0 www.fairchildsemi.com FXL3SD206 -- Level Shifting Voltage Translator Application Diagrams Power Management IC VDDA VDD_CON VDD_HI VDD Select Card Select HOST VDD_SEL CH_SEL In MUX Out In VDD_LO VDD_HI SD Card 1CLK CMD_B CMD B 1D0~D3 VDD_LO SDIO Device WiFi LAN / Bluetooth / Memory Module CMD Output Enable CMD_ A OE Out DEMUX In Out 2CLK CMD_C CMD C 2D0~D3 CLK D0~D3 CLK_A D0_A~D3_A CLK_BC D0_BC~D3_BC Figure 1. Single Host to Two SDIO Application Diagram Power Management IC VDDA VDD_CON VDD SEL OE CH SEL VDD_LO VDD_HI VDD Select Output Enable Card Select SD Memory Or SDIO Device CMD CMD A 1CLK In MUX Out In VDD_HI CMD B CMD B 1D0~D3 Application Processor Out In DEMUX Out 2CLK CMD C VDD_LO Baseband Processor CMD C 2D0~D3 CLK D0~D3 CLK_A D0_A~D3_A CLK_BC D0_BC~D3_BC Figure 2. Dual Host to Single SDIO Application (c) 2009 Fairchild Semiconductor Corporation FXL3SD206 * Rev. 1.0.0 www.fairchildsemi.com 2 FXL3SD206 -- Level Shifting Voltage Translator Pin Configuration 18 19 13 12 24 1 6 7 Figure 3. Pin Configuration (Top Through View) Pin Definitions Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Name D0_A D1_A D2_A D3_A CLK_A ---CMD_A ---GND CMD_C ---CMD_B CLK_BC D3_BC D2_BC D1_BC D0_BC VDD_LO VDD_HI VDD_CON VDDA VDD_SEL CH_SEL OE Type Data Data Data Data Data NC Data NC Power Data NC Data Data Data Data Data Data Power Power Power Power Control Control Control Description Data Pin of A Port Data Pin of A Port Data Pin of A Port Data Pin of A Port Clock Pin of A Port No Connect Command Pin of A Port No Connect Ground Command Pin of C Port No Connect Command Pin of B Port Clock Pin of B or C Port Data Pin of B or C Port Data Pin of B or C Port Data Pin of B or C Port Data Pin of B or C Port B or C Port, Low Power Supply B or C Port, High Power Supply Control Pin Power Supply A-Port Power Supply Power Supply Select Pin of B and C Ports Channel Select Pin Output Enable Pin (c) 2009 Fairchild Semiconductor Corporation FXL3SD206 * Rev. 1.0.0 www.fairchildsemi.com 3 FXL3SD206 -- Level Shifting Voltage Translator Function Diagram Figure 4. Function Diagram Function Table OE LOW HIGH HIGH HIGH HIGH CH_SEL Don't Care HIGH HIGH LOW LOW VDD_SEL Don't Care HIGH LOW HIGH LOW 3-State Output Normal operation; Port A to Port B channel selected; Port B tracks VDD_HI level Normal operation; Port A to Port B channel selected; Port B tracks VDD_LO level Normal operation; Port A to Port C channel selected; Port C tracks VDD_HI level Normal operation; Port A to Port C channel selected; Port C tracks VDD_LO level Note: 1. VDD_CON: This is a power supply pin that is used by the three control pins (VDD_SEL, CH_SEL, and OE). In single host mode, VDD_CON should be tied to the same supply as the VDDA pin. In dual host mode, VDD_CON should be tied to the same supply as either the VDD_HI or the VDD_LO pin, depending upon which host is used to drive the control pins. (c) 2009 Fairchild Semiconductor Corporation FXL3SD206 * Rev. 1.0.0 www.fairchildsemi.com 4 FXL3SD206 -- Level Shifting Voltage Translator Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VDD VI Parameter Supply Voltage DC Input Voltage Conditions VDDA, VDD_HI, VDD_LO, VDD_CON Data Ports A, B, and C Control Inputs (OE, CH_SEL, VDD_SEL) Output 3-State Output Active (Port A) Output Active (Port B or C) Output Active (Port B or C) VI<0V VO<0V VO>VCC Min. -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 Max. 4.6 4.6 4.6 4.6 VDDA+0.5 VDD_HI+0.5 VDD_LO+0.5 -50 -50 +50 Unit V V V VO Output Voltage (2) V IIK IOK IOH/IOL IDD TSTG DC Input Diode Current DC Output Diode Current DC Output Source/Sink Current mA mA mA mA C -50 -65 +50 100 +150 DC VDD or Ground Current per Supply Pin Storage Temperature Range Note: 2. IO absolute maximum rating must be observed. Recommended Operating Conditions (3) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VDD Parameter Power Supply Operating Conditions VDDA, VDD_HI, VDD_LO, VDD_CON VDD_HI VDD_LO Port A Port B and C Port B and C (5) (5) (4) Min. 1.65 0 0 0 -40 Max. 3.60 VDDA VDD_HI VDD_LO +85 10 10 10 Unit V VIN TA Input Voltage Free Air Operation Temperature V C Data Port A at VDDA=1.65 to 3.6V dt/dV Minimum Input Edge Rate Data Ports B and C at VDD_n=1.65 to 3.6V OE, CH_SEL, VDD_SEL at VDD_CON=1.65V to 3.6V ns/V Notes: 3. All unused inputs and input/outputs must be held at VDDn or GND. 4. During normal operation, VDD_HI must be greater than or equal to VDD_LO. 5. The input and output voltages of Ports B and C are determined by which VDD is selected. (c) 2009 Fairchild Semiconductor Corporation FXL3SD206 * Rev. 1.0.0 www.fairchildsemi.com 5 FXL3SD206 -- Level Shifting Voltage Translator Application Information Power-Up / Power-Down Sequencing FXL translators offer an advantage in that any VDD may be powered up first. This benefit derives from the chip design. When VDDA or both VDD_HI and VDD_LO pins are at 0 volts, outputs are in a high-impedance state (see Power Up Operation table below). As a multiplexer, the device allows the unselected port to remain in a high-impedance state for power saving. The control inputs (OE, CH_SEL, VDD_SEL) are designed to track VDD_CON. An external pull-down resistor tying OE to GND should be used to ensure that bus contention, excessive current, or oscillations do not occur during power-up/power-down. The size of the pull-down resistor is based upon the current-sinking capability of the device driving the OE pin. During normal operation, VDD_HI must be greater than or equal to VDD_LO. During power-up or power-down, VDD_LO may exceed VDD_HI without damaging the device. The recommended power-up sequence is: 1. 2. 3. 4. Apply the power to the first VDD. Apply the power to the second VDD. Set the CH_SEL and VDD_SEL pin according to the application. Drive the OE input high to enable the device. The recommended the power-down sequence is: 1. 2. 3. 4. Drive the OE input low to disable the device. Remove the setting of CH_SEL and VDD_SEL pin. Remove power from either VDD. Remove power from other VDD. Table 1. VDDA OFF ON ON ON ON Power-Up Operation VDD_HI Don't Care OFF ON OFF ON VDD_LO Don't Care OFF OFF ON ON VDD_SEL Don't Care Don't Care HIGH LOW HIGH LOW HIGH LOW Port B or C Outputs High Impedance High Impedance Enabled, Reference to VDD_HI High Impedance High Impedance Enabled, Reference to VDD_LO Enabled, Reference to VDD_HI Enabled, Reference to VDD_LO (c) 2009 Fairchild Semiconductor Corporation FXL3SD206 * Rev. 1.0.0 www.fairchildsemi.com 6 FXL3SD206 -- Level Shifting Voltage Translator DC Electrical Characteristics TA=-40C to 85C unless otherwise specified. Symbol VIHA VIHB VIHC VIH VILA VILB VILC VIL VOHA VOHB VOHC VOLA VOLB VOLC Parameter Condition Data Inputs Dn_A, CMD_A, CLK_A, VDD_A, VDD_n, (V) 1.65 - 3.6 1.65 - 3.6 1.65 - 3.6 Min. 0.6 x VDD_A 0.6 x VDD_n 0.6 x VDD_n Max. Units V V V V High Level Input (6) Voltage Data Inputs Dn_BC, CMD_B, CLK_BC, CH_SEL=H Data Inputs Dn_BC, CMD_C, CLK_BC, CH_SEL=L OE, VDD_SEL, CH_SEL Data Inputs Dn_A, CMD_A, CLK_A, Data Inputs Dn_BC, CMD_B, CLK_BC, CH_SEL=H Data Inputs Dn_BC, CMD_C, CLK_BC, CH_SEL=L OE, VDD_SEL, CH_SEL Data Outputs Dn_A, CMD_A, CLK_A, IHOLD=-20A 1.65 - 3.6 0.6 x VDD_CON 1.65 - 3.6 1.65 -3.6 1.65 -3.6 1.65 - 3.6 1.65 - 3.6 0.75 x VDD_A 1.65 - 3.6 1.65 - 3.6 0.75 x VDD_n 0.75 x VDD_n 0.35 x VDD_A 0.35 x VDD_n 0.35 x VDD_n 0.35 x VDD_CON V V V V V V V V V V Low Level Input (6) Voltage High Level Output (6, 7) Voltage Data Outputs Dn_BC, CMD_B, CLK_BC, CH_SEL=H, IHOLD=-20A Data Outputs Dn_BC, CMD_B, CLK_BC, CH_SEL=L, IHOLD=-20A Data Outputs Dn_A, CMD_A, CLK_A, IHOLD=+20A 1.65 - 3.6 0.25 x VDD_A 1.65 - 3.6 1.65 - 3.6 0.25 x VDD_n 0.25 x VDD_n Low Level Output (6, 7) Voltage Data Outputs Dn_BC, CMD_B, CLK_BC, CH_SEL=H, IHOLD=+20A Data Outputs Dn_BC, CMD_B, CLK_BC, CH_SEL=L, IHOLD=+20A Notes: 6. Port B and Port C share the same data and clock pin, and VDD_n refers to VDD_HI or VDD_LO, whichever is selected. During normal operation, VDD_HI must be greater than or equal to VDD_LO. 7. This is the output voltage for static conditions. Dynamic drive specifications are given in "Dynamic Output Electrical Characteristics. (c) 2009 Fairchild Semiconductor Corporation FXL3SD206 * Rev. 1.0.0 www.fairchildsemi.com 7 FXL3SD206 -- Level Shifting Voltage Translator DC Electrical Characteristics (Continued) TA=-40C to 85C unless otherwise specified. Symbol IIODH Parameter Condition VDD_A (V) 3.6 2.7 1.95 3.6 VDD_n (V) 3.6 2.7 1.95 3.6 2.7 1.95 3.6 3.6 0 3.6 0 3.6 1.65 - 3.6 1.65 - 3.6 0 1.65 - 3.6 Min. Max. Units 450 300 200 -450 -300 -200 1.0 2.0 2.0 2.0 2.0 2.0 5.0 2.0 2.0 5.0 A A A A A A A A A A A A A A A A Bushold Input Data Inputs Dn_A, CMD_A, CLK_A Overdrive High Dn_BC, CMD_B, CMD_C, CLK_BC (8) Current Bushold Input Overdrive Low (9) Current Input Leakage Current Power Off Leakage Current IIODL Data Inputs Dn_A, CMD_A, CLK_A Dn_BC, CMD_B, CMD_C, CLK_BC Control Inputs OE, CH_SEL, VDD_SEL, VI=VDD_CON or GND Dn_A, CMD_A, CLK_A; VO=0 to 3.6V Dn_BC, CMD_B, CMD_C, CLK_BC; VO=0 to 3.6V Dn_A, CMD_A, CMD_B, CMD_C, Dn_BC, CLK_A, CLK_BC; VO=0V or 3.6V; OE=VIL Dn_A, CMD_A, CLK_BC; VO=0V or (10) 3.6V; OE=Don't Care Dn_BC, CMD_B, CMD_C, CLK_BC; (10) VO=0V or 3.6V; OE=Don't Care 2.7 1.95 1.65 -3.6 0 3.6 3.6 3.6 0 1.65 - 3.6 II IOFF IOZ 3-state Output Leakage ICC Quiescent Supply (11, 12) Current Quiescent Supply (11) Current VI=VDDI or GND; IO=0 0 1.65 - 3.6 ICCZ VI=VDDI or GND; IO=0, OE=VIL 1.65 - 3.6 Notes: 8. An external driver must source at least the specified current to switch LOW-to-HIGH. 9. An external driver must source at least the specified current to switch HIGH-to-LOW. 10. "Don't care" indicates any valid logic level. 11. VDDI is the VDD associated with the input side. 12. Reflects current per supply, VDD_A or VDD_n. (c) 2009 Fairchild Semiconductor Corporation FXL3SD206 * Rev. 1.0.0 www.fairchildsemi.com 8 FXL3SD206 -- Level Shifting Voltage Translator Dynamic Output Electrical Characteristics A Port (Dn_A, CMD_A, CLK_A), B and C Port (CMD_B, CMD_C) Output Load: CL=15pF, RL 1M (CI/O=10pF). TA=-40C to 85C. Symbol trise tfall IOHD IOLD Parameter Output Rise Time A Port Output Fall Time A Port (13) VDD=2.8V to 3.6V VDD=2.3V to 2.7V VDD=1.65V to1.95V Typ. (14) (13) Units ns ns mA mA Max. 3.0 3.0 Typ. Max. 3.5 3.5 Typ. Max. 4.0 4.0 Dynamic Output Current High Dynamic Output Current Low -14.0 +14.0 -10.0 +10.0 -6.2 +6.2 (14) B and C Port (Dn_BC, CLK_BC) Output Load: CL=30pF, RL 1M (CI/O=10pF). TA=-40C to 85C. Symbol trise tfall IOHD IOLD Parameter Output Rise Time B and C (13) Port Output Fall Time B and C Port Dynamic Output Current High Dynamic Output Current Low (14) (13) VDD=2.8V to 3.6V VDD=2.3V to 2.7V VDD=1.65V to 1.95V Typ. Max. 3.0 3.0 -22.4 +22.4 -15.8 +15.8 Units ns ns mA mA Typ. Max. 3.5 3.5 Typ. Max. 4.0 4.0 -10.0 +10.0 (14) Notes: 13. See Figure 9. 14. See Figure 10. (c) 2009 Fairchild Semiconductor Corporation FXL3SD206 * Rev. 1.0.0 www.fairchildsemi.com 9 FXL3SD206 -- Level Shifting Voltage Translator AC Characteristics VDD_A=2.8V to 3.6V and TA=-40C to 85C. Symbol tPLH, tPHL tPZL, tPZH tPCH tskew Parameter A to B/C B/C to A OE to A OE to B/C CH_SEL B to C or C to B A, B, C Port (15) VDD_n=2.8V to 3.6V Min. 0.2 0.2 VDD_n=2.3V to 2.7V VDD_n=1.65V to 1.95V Min. 0.3 0.2 Units ns ns s s ns Max. 3.5 3.5 1.7 1.7 0.5 Max. 3.9 3.8 1.7 1.7 0.5 Min. 0.5 0.3 Max. 5.4 5.0 1.7 1.7 1.0 VDD_A=2.3V to 2.7V and TA=-40C to 85C. Symbol tPLH, tPHL tPZL, tPZH tPCH tskew Parameter A to B/C B/C to A OE to A OE to B/C CH_SEL B to C or C to B A, B, C Port (15) VDD_n=2.8V to 3.6V Min. 0.2 0.3 VDD_n=2.3V to 2.7V VDD_n=1.65V to 1.95V Min. 0.4 0.4 Units ns ns s s ns Max. 3.8 3.9 1.7 1.7 0.5 Max. 4.5 4.5 1.7 1.7 0.5 Min. 0.5 0.5 Max. 5.6 5.5 1.7 1.7 1.0 VDD_A=1.65V to 1.95V and TA=-40C to 85C. Symbol tPLH, tPHL tPZL, tPZH tPCH tskew Parameter A to B/C B/C to A OE to A OE to B/C CH_SEL B to C or C to B A, B, C Port (15) VDD_n=2.8V to 3.6V Min. 0.3 0.5 VDD_n=2.3V to 2.7V VDD_n=1.65V to 1.95V Min. 0.5 0.5 Units ns ns s s ns Max. 5.0 5.4 1.7 1.7 1.0 Max. 5.5 5.6 1.7 1.7 1.0 Min. 0.8 0.8 Max. 6.7 6.7 1.7 1.7 1.0 Note: 15. Skew is the variation of propagation delay between output signals and applies only to output signals on the same port and switching with the same polarity (LOW to HIGH or HIGH to LOW). See Figure 12. Skew is guaranteed, but not tested. (c) 2009 Fairchild Semiconductor Corporation FXL3SD206 * Rev. 1.0.0 www.fairchildsemi.com 10 FXL3SD206 -- Level Shifting Voltage Translator Maximum Data Rate(16) TA=-40C to 85C. VDD_A VDD_A=2.8 to 3.6V VDD_A=2.3 to 2.7V VDD_A=1.65 to 1.95V Direction A to B/C B/C to A A to B/C B/C to A A to B/C B/C to A VDD_n=2.8V to 3.6V Min. 100 100 100 100 80 80 VDD_n=2.3V to 2.7V VDD_n=1.65V to 1.95V Min. 100 100 100 100 80 80 Units Mbps Mbps Mbps Min. 80 80 80 80 60 60 Note: 16. Maximum Data Rate is specified in megabits per second. See Figure 11. It is equivalent to two times the fTOGGLE frequency, specified in megahertz. For example, 100Mbps is equivalent to 50MHZ. Capacitance TA=+25C. Symbol CIN CI/O CPD Parameter Input Capacitance Control Pins (OE, VDD_SEL, CH_SEL) Input/Output Capacitance Dn_A, CMD_A,CLK_A Dn_BC, CMD_B, CMD_C, CLK_BC Conditions VDD_CON=GND VDD_A=VDD_n=3.3V, OE=VDD_A, CH_SEL=VDD_A or GND VDD_A=VDD_n=3.3V, VI=0V or VDD, f=10MHZ Typical 4.0 5.0 6.5 25 Units pF pF pF Power Dissipation Capacitance (c) 2009 Fairchild Semiconductor Corporation FXL3SD206 * Rev. 1.0.0 www.fairchildsemi.com 11 FXL3SD206 -- Level Shifting Voltage Translator Test Diagrams VCC TEST SIGNAL DUT C1 R1 Figure 5. AC Test Circuit Table 2. AC Test Conditions Test tPLH, tPHL tPZL tPZH Input Signal Data Pulses 0V VCCI Output Enable Control VI=VDD_CON LOW to HIGH Switch LOW to HIGH Switch Table 3. AC Load VCCo CL Port A, CMD_B, CMD_C 15pF 15pF 15pF Dn_BC, CLK_BC 30pF 30pF 30pF RL Port A, B, or C 1M 1M 1M Port A, B, or C 1.8V 0.15V 2.5V 0.2V 2.8V to 3.6V DATA IN tpxx DATA OUT Vmi tpxx Vmo VCCI GND VCCO Figure 6. Waveform for Inverting and Non-Inverting Functions Notes: 17. Input tR = tF = 2.0ns, 10% to 90%. 18. Input tR = tF = 2.5ns, 10% to 90%, at VI = 3.0V to 3.6V only. (c) 2009 Fairchild Semiconductor Corporation FXL3SD206 * Rev. 1.0.0 www.fairchildsemi.com 12 FXL3SD206 -- Level Shifting Voltage Translator OUTPUT CONTROL tPZL DATA OUT Vmi VCC_CON GND VY VOL Figure 7. 3-State Output Low Enable Time for Low Voltage Logic Notes: 19. Input tR = tF = 2.0ns, 10% to 90%. 20. Input tR = tF = 2.5ns, 10% to 90%, at VI = 3.0V to 3.6V only. OUTPUT CONTROL tPZH DATA OUT Vmi VCC_CON GND VOH Vx Figure 8. 3-State Output High Enable Time for Low Voltage Logic Notes: 21. Input tR = tF = 2.0ns, 10% to 90%. 22. Input tR = tF = 2.5ns, 10% to 90%, at VI = 3.0V to 3.6V only. Symbol VMI VMO VX VY VDD VDDI /2 VDDo /2 0.9 x VDDo 0.1 x VDDo (c) 2009 Fairchild Semiconductor Corporation FXL3SD206 * Rev. 1.0.0 www.fairchildsemi.com 13 FXL3SD206 -- Level Shifting Voltage Translator trise VOH 80% x VCCO VOUT 20% x VCCO Time IOHD (CL + CI / O ) x VOUT (20% - 80%) * VCCO = (CL + CI / O ) x t t RISE VOL Figure 9. Active Output Rise Time and Dynamic Output Current High VOH 80% x VCCO VOUT tfall 20% x VCCO Time IOHD (CL + CI / O ) x Figure 10. VOL VOUT (80% - 20%) * VCCO = (CL + CI / O ) x t t FALL Active Output Fall Time and Dynamic Output Current Low tW DATA IN VCCI/2 VCCI/2 VCCI GND Maximum Data Rate, f = 1/tW Figure 11. Maximum Data Rate DATA OUTPUT tskew DATA OUTPUT VCCO Vmo Vmo tskew VCCO Vmo Vmo GND GND tskew = (tpHLmax - tpHLmin) or (tpLHmax - tpLHmin) Figure 12. (c) 2009 Fairchild Semiconductor Corporation FXL3SD206 * Rev. 1.0.0 Output Skew Time www.fairchildsemi.com 14 FXL3SD206 -- Level Shifting Voltage Translator Physical Dimensions 2.80 2.23 0.10 C 0.66 2.50 0.56 2X A B 1 24 19 0.40 PIN #1 IDENT 2.23 3.40 13 3.70 0.10 C 7 TOP VIEW 2X 0.23 RECOMMENDED LAND PATTERN 0.55 MAX. 0.10 C 0.08 C 0.05 0.00 0.15 SEATING PLANE C SIDE VIEW 7 23X 0.35 0.45 13 0.40 1 0.45 0.55 24 19 0.15 24X 0.25 0.10 C A B 0.05 C BOTTOM VIEW Figure 13. 24-Pin, Micro-MLP, Quad, .6mm Thick, 2.5mm x 3.4mm Body Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. (c) 2009 Fairchild Semiconductor Corporation FXL3SD206 * Rev. 1.0.0 www.fairchildsemi.com 15 FXL3SD206 -- Level Shifting Voltage Translator (c) 2009 Fairchild Semiconductor Corporation FXL3SD206 * Rev. 1.0.0 www.fairchildsemi.com 16 |
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